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DATA SHEET
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column Display Data Memory
To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products
data sheet (v6.3)
2006 Aug 16
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
1 1.1
GENERAL Description
The SBN1661G_X is a series of STN LCD SEGMENT/COMMON drivers. The series has four members: * the SBN1661G_M18, * the SBN1661G_M02, * the SBN0080G_S18, and * the SBN0080G_S02. Both the SBN1661G_M18 and the SBN1661G_M02 can drive 16 COMMONs and 61 SEGMENTs and can be used as master in a master-slave connection. They both have 32-row x 80-column Display Data Memory. Functionally, their only difference is that the SBN1661G_M18 has an on-chip RC-type oscillator and can provide clock to slave, while the SBN1661G_M02 does not have an on-chip oscillator and needs external clock source. Both the SBN0080G_S18 and the SBN0080G_S02 are purely SEGMENT drivers. They do not have COMMON outputs and are used for segment expansion in a master-slave connection. Both devices need either a master or an external clock source to provide clock. The only difference between these two chips is their operating frequency. The SBN0080G_S18's operating frequency is 18 KHz, while the SBN0080G_S02's operating frequency is 2KHz. All four devices have on-chip Display Data Memory of 32-rows x 80-columns, for storing display data. Dot-matrix mapping method is used to drive the LCD panel. Therefore, a bit of the Display Data Memory corresponds to a pixel on the LCD panel. SEGMENT drivers provide display data to the LCD panel and COMMON drivers provide row-scanning signal. All four devices have a set of internal registers. These internal registers must be properly programmed to ensure proper operation of the devices. Display on the LCD panel is controlled by a host microcontroller. All four devices communicate with the host microcontroller via data bus and control bus. The data bus is 8-bit wide. The control bus are READ, WRITE, and Chip Select. The host microcontroller can perform READ/WRITE operations to the internal registers and Display Data RAM of all four devices. A wide variety of microcontrollers can easily interface with the devices, as the devices can accept both 80-type interface timing and 68-type interface timing. The selection of interface timing is via the dual-function RESET/IF pin.
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
1.2
Features
* Four members of the SBN1661G_X series: - the SBN1661G_M18, - the SBN1661G_M02, - the SBN0080G_S18, and - the SBN0080G_S02 * 16 COMMON, 61 SEGMENT STN LCD driver (the SBN1661G_M18 and the SBN1661G_M02). * 80 SEGMENT STN LCD driver for expanding segment number (the SBN0080G_S18 and the SBN0080G_S02). * On-chip Display Data Memory: 32-row x 80-column (totally 2560 bits). * Dot Matrix Mapping between the Display Data Memory bit and LCD pixel. * A "0" stored in the Display Data Memory bit corresponds to an OFF-pixel on the LCD panel; a "1" stored in the Display Data Memory bit corresponds to an ON-pixel on the LCD panel. * 5-level external LCD bias. * Display duty cycle: 1/16, 1/32 for all four devices. * Two types of interface timing with a host microcontroller: the 80-type microcontroller and the 68-type microcontroller. * Dual function RESET/IF input for chip reset and selection of microcontroller interface timing. * 8-bit parrallel data bus; READ, WRITE, CHIP SELECT control bus. * A set of internal registers: Display ON/OFF, Display Start Line, Static Drive ON/OFF, Memory Page Address, Memory Column Address, Duty Selection, Memory Column/Segment mapping, and Status. * Display Data Read/Write commands and Software Reset command. * Read-Modify-Write command for block data transfer from the host microcontroller to the Display Data Memory. * Power-saving mode. * On-chip RC-type oscillator, requiring only an external resistor (the SBN1661G_M18). * Operating voltage range (VDD): 2.7 ~ 5.5 volts. * LCD bias voltage (VLCD=V5-VDD): -13 volts (max.). * Operating frequency range: 2 KHz, 18 KHz. * Operating temperature range: -20 to +75 C. * Storage temperature range: -55 to +125 C.
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
1.3
Ordering information Product types Clock frequency on-chip SBN1661G_M18 SBN1661G_M02 SBN0080G_S18 SBN0080G_S02 18 KHz External 18 KHz 2 KHz 18 KHz 2 KHz Number of segment driver 61 80 Number of common driver 16 1/16, 1/32 0 duty cycle
Table 1
Product Name
Table 2
Ordering information PRODUCT TYPE DESCRIPTION LQFP100 Pb-free package. QFP100 Pb-free package. LQFP100 general package. QFP100 general package. tested die. LQFP100 Pb-free package. QFP100 Pb-free package. LQFP100 general package. QFP100 general package. tested die. LQFP100 Pb-free package. QFP100 Pb-free package. LQFP100 general package. QFP100 general package. tested die. LQFP100 Pb-free package. QFP100 Pb-free package. LQFP100 general package. QFP100 general package. tested die.
SBN1661G_M18-LQFPG SBN1661G_M18-QFPG SBN1661G_M18-LQFP SBN1661G_M18-QFP SBN1661G_M18-D SBN1661G_M02-LQFPG SBN1661G_M02-QFPG SBN1661G_M02-LQFP SBN1661G_M02-QFP SBN1661G_M02-D SBN0080G_S18-LQFPG SBN0080G_S18-QFPG SBN0080G_S18-LQFP SBN0080G_S18-QFP SBN0080G_S18-D SBN0080G_S02-LQFPG SBN0080G_S02-QFPG SBN0080G_S02-LQFP SBN0080G_S02-QFP SBN0080G_S02-D
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
2 2.1
FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION Funtional block diagram (SBN1661G_M18, SBN1661G_M02) COM15 SEG60 SEG59 COM1 COM0
SEG1 OSC2(CL)
V5 V4 V3 V2 V1
High Voltage Circuit
Output Driver Level Shifter
MUX
Display Control Time Gen.
COMMON Counter
Mapping Circuit
C/S Mappig Register Display ON/OFF Register Display Start Line Register Page Address Register Column Address Register Status Register Duty Select Register Static Drive ON/OFF Register Line Address Decoder
Display Data RAM Buffer 32 row x 80 column (2560 bits) Display Data RAM
Column Address Decoder
Command Decoder
Display Data RAM Access Control
Display Control
Display Data Read/Write Control
Microcontroller Interface
OSC and Timing Gen.
OSC1(CS)
DB0~DB7
R/W(WR)
RESET/IF
E/RD
M/S
C/D
FR
Fig.1 Functional Block Diagram
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SEG0
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3 3.1
PIN(PAD) ASSIGNMENT, PAD COORDINATES, SIGNAL DESCRIPTION The SBN1661G_M18 and SBN1661G_M02 pinning diagram (LQFP100)
DB2 DB3 DB4 DB5 DB6 DB7 VDD RESET/IF FR V5 V3 V2 M/S V4 V1 COM0 COM1 COM2 COM3 COM4
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DB1 DB0 VSS R/W(WR) E/RD OSC2(CL) OSC1(CS) C/D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41
SBN1661G_M18 SBN1661G_M02
(Master/Slave Driver)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 Note: (1) For the SBN1661G_M18, pin 74 is OSC1 and pin 75 is OSC2. (2) For the SBN1661G_M02, pin 74 is CS and pin 75 is CL. (3) All other pins of both devices have the same pin(pad) assignment. (4) Both devices can be used as master or slave, by setting their M/S pin.
Fig.2 The SBN1661G_M18 , the SBN1661G_M02 pin assignment of LQFP100 package.
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3.2
The SBN0080G_S18, the SBN0080G_S02 pinning diagram (LQFP100)
DB2 DB3 DB4 DB5 DB6 DB7 VDD RESET/IF FR V5 V3 V2 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DB1 DB0 VSS R/W(WR) E/RD CL CS C/D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41
SBN0080G_S18 SBN0080G_S02
(Slave Segment Driver)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 Note: (1) Both devices have the same pin(pad) assignment. (2) Both devices can be used only as Slave Segment Driver.
Fig.3 The SBN0080G_S18, the SBN0080G_S02 pin assignment of LQFP100 package.
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3.3
The SBN1661G_M18 , SBN1661G_M02 pad placement
100 COM4
88 RESET/IF
99 COM3
98 COM2
97 COM1 96 COM0
87 VDD
80 DB1 79 DB0 78 VSS 77 R/W(WR) 76 E/RD 75 OSC2(CL) 74 OSC1(CS) 73 C/D 72 SEG0 71 SEG1 70 SEG2 69 SEG3 68 SEG4 67 SEG5 66 SEG6 65 SEG7 64 SEG8 63 SEG9 62 SEG10 61 SEG11 60 SEG12 59 SEG13 58 SEG14 57 SEG15 56 SEG16 55 SEG17 54 SEG18 53 SEG19 52 SEG20 51 SEG21 50 SEG22
86 DB7
85 DB6
84 DB5
82 DB3 48 SEG24
83 DB4 47 SEG25
COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13
1 2 3 4 5 6 7 8 9
COM14 10 COM15 11 SEG60 12 SEG59 13 SEG58 14 SEG57 15 SEG56 16 SEG55 17 SEG54 18 SEG53 19 SEG52 20 SEG51 21 SEG50 22 SEG49 23 SEG48 24 SEG47 25 SEG46 26 SEG45 27 SEG44 28 SEG43 29 SEG42 30 31 SEG41 32 SEG40 33 SEG39 34 SEG38 35 SEG37 36 SEG36 38 SEG34 37 SEG35 39 SEG33 40 SEG32 41 SEG31 42 SEG30 43 SEG29 44 SEG28 45 SEG27 46 SEG26 49 SEG23
Y
(0,0)
X
chip size : 4162 m x 3000 m. Pad size: 90 m x 90 m.
Note: (1) The SBN1661G_M18 and the SBN1661G_M02 have the same pad placement. (2) The chip ID of the SBN1661G_M18 is AT18001-01. (3) The chip ID of the SBN1661G_M02 is AT18001-02. (4) The die origin is at the center of the chip. (5) For chip_on_board_bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which the die is attached.
Fig.4 The SBN1661G_M18, SBN1661G_M02 pad placement
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81 DB2
93 M/S 92 V2
89 FR
95 V1 94 V4
91 V3
90 V5
chip ID
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3.4
The SBN0080G_S18 , SBN0080G_S02 pad placement
100 SEG72
88 RESET/IF
99 SEG73
98 SEG74
97 SEG75 96 SEG76
95 SEG77 94 SEG78
93 SEG79 92 V2
87 VDD
80 DB1 79 DB0 78 VSS 77 R/W(WR) 76 E/RD 75 CL 74 CS 73 C/D 72 SEG0 71 SEG1 70 SEG2 69 SEG3 68 SEG4 67 SEG5 66 SEG6 65 SEG7 64 SEG8 63 SEG9 62 SEG10 61 SEG11 60 SEG12 59 SEG13 58 SEG14 57 SEG15 56 SEG16 55 SEG17 54 SEG18 53 SEG19 52 SEG20 51 SEG21 50 SEG22
86 DB7
85 DB6
84 DB5
82 DB3 48 SEG24
83 DB4 47 SEG25
SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63
1 2 3 4 5 6 7 8 9
SEG62 10 SEG61 11 SEG60 12 SEG59 13 SEG58 14 SEG57 15 SEG56 16 SEG55 17 SEG54 18 SEG53 19 SEG52 20 SEG51 21 SEG50 22 SEG49 23 SEG48 24 SEG47 25 SEG46 26 SEG45 27 SEG44 28 SEG43 29 SEG42 30 31 SEG41 32 SEG40 33 SEG39 34 SEG38 35 SEG37 36 SEG36 38 SEG34 37 SEG35 39 SEG33 40 SEG32 41 SEG31 42 SEG30 43 SEG29 44 SEG28 45 SEG27 46 SEG26 49 SEG23
Y
(0,0)
X
chip size : 4162 m x 3000 m. Pad size: 90 m x 90 m.
Note: (1) The SBN0080G_S18 and the SBN0080G_S02 have the same pad placement. (2) The chip ID of the SBN0080G_S18 is AT18001-03 (3) The chip ID of the SBN0080G_S02 is AT18001-04. (4) The die origin is at the center of the chip. (5) For chip_on_board_bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which the die is attached.
Fig.5 The SBN0080G_S18, SBN0080G_S02 pad placement
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81 DB2
89 FR
91 V3
90 V5
chip ID
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3.5
The SBN1661G_M18, SBN1661G_M02 pad coordinates The SBN1661G_M18, SBN1661G_M02 pad coordinates (unit: m) PAD NAME COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 X -1824 -1694 -1569 -1444 -1319 -1186 -1053 -920 -787 -654 -521 -388 -255 -122 11 144 277 410 543 676 809 942 1075 1208 1341 1474 1607 1740 1873 2006 2011 2011 2011 2011 Y -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1272 -1137 -1002 -867 PAD NO. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PAD NAME SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 X 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 1842 1712 1582 1452 1322 1192 1062 932 802 672 542 412 282 152 22 -108 -238 -368 Y -732 -597 -462 -327 -192 -57 78 213 348 483 618 753 883 1013 1143 1273 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 PAD PAD NO. NAME 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG3 SEG2 SEG1 SEG0 C/D OSC1 OSC2 E/RD R/W(WR) VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD FR V5 V3 V2 M/S V4 V1 COM0 COM1 COM2 COM3 COM4 X -498 -628 -758 -888 -1062 -1194 -1326 -1458 -1590 -1722 -1854 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 Y 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1358 1176 1044 909 771 635 497 358 212 81 -50 -180 -326 -456 -586 -716 -846 -976 -1106 -1236 -1388
Table 3 PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
RESET/IF -2011
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3.6
The SBN0080G_S18, SBN0080G_S02 pad coordinates The SBN0080G_S18, SBN0080G_S02 pad coordinates ( unit: m ) Pad Name SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 X -1824 -1694 -1569 -1444 -1319 -1186 -1053 -920 -787 -654 -521 -388 -255 -122 11 144 277 410 543 676 809 942 1075 1208 1341 1474 1607 1740 1873 2006 2011 2011 2011 2011 Y -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1430 -1272 -1137 -1002 -867 Pad No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pad Name SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 X 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 1842 1712 1582 1452 1322 1192 1062 932 802 672 542 412 282 152 22 -108 -238 -368 Y -732 -597 -462 -327 -192 -57 78 213 348 483 618 753 883 1013 1143 1273 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 Pad No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name X SEG3 SEG2 SEG1 SEG0 C/D CS CL E/RD R/W(WR) VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD RESET/IF FR V5 V3 V2 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 -498 -628 -758 -888 -1062 -1194 -1326 -1458 -1590 -1722 -1854 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 -2011 Y 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1430 1358 1176 1044 909 771 635 497 358 212 81 -50 -180 -326 -456 -586 -716 -846 -976 -1106 -1236 -1388
Table 4 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3.7
Pin(pad) signal difference among the four members of the SBN1661G_X
All four members of the SBN1661G_X series have the same pad sequence and placement. However, some pins(pads) have different signals for different types. A comparison is given in Table 5. Table 5 Type SBN1661G_M18 SBN1661G_M02 SBN0080G_S18 SBN0080G_S02 3.8 Comparison of pin(pad) signals Pin(pad) 1~11 COM5~15 COM5~15 SEG71~61 Pin(pad) 74 OSC1 CS CS Pin(pad) 75 OSC2 CL CL Pin(pad) 93 M/S M/S SEG79 Pin(pad) 94 V4 V4 SEG78 Pin(pad) 95 V1 V1 SEG77 Pin(pad) 96~100 COM0~4 COM0~4 SEG76~72
Pin (pad) states after hardware RESET Pin(pad) states after RESET
Table 6
SBN1661G_M18, SBN1661G_M02 signal DB0~DB7 COM0~COM15 SEG0~SEG61 FR(SBN1661G_M18) OSC2 (SBN1661G_M18) states after RESET tri-state VDD VDD tri-state tri-state
SBN0080G_S18, SBN0080G_S02 signal DB0~DB7 SEG0~SEG79 states after RESET tri-state VDD
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
3.9
The SBN1661G_M18 and the SBN1661G_M02 signal description
Table 7 Pin (pad) signal description To avoid a latch-up effect at power-on: VSS - 0.5 V < voltage at any pin at any time < VDD + 0.5 V . Pin number SYMBOL I/O COMMON driver outputs. The output voltage level of COMMON outputs are decided by the combination of the alternating frame signal (FR) and the internal COMMON COUNTER, which generates raster-scanning COMMON signals. Depending on the value of the frame signal and the COMMON counter output, a single voltage level is selected from VDD, V1, V4, or V5 for COMMON driver , as shown in Fig. 6. DESCRIPTION
1~11, 96~100
COM5~15, COM0~4
Output
FR Common Counter output COMMON output
0
1
0
1
0
0 V4
1 V5
0 V1
1 VDD
0 V4
1 V5
0 V1
1 VDD
Fig.6 COMMON driver output voltage level
SEGNENT driver outputs. The output voltage level of SEGMENT outputs are decided by the combination of the alternating frame signal (FR) and display data. Depending on the value of the frame signal and the display data, a sinlge voltage level is selected from VDD, V2, V3, or V5 for SEGMENT driver, as shown in Fig. 7.
12~72
SEG60~0
Output
FR
0
1
0
1
0
Display Data bit SEG output
0 V3
1 VDD
0 V2
1 V5
0 V3
1 VDD
0 V2
1 V5
Fig.7 SEGMENT driver output voltage level
Selection of command or data. When C/D=0, the data on the 8-bit data bus (DB0~DB7) are either COMMAMD, data to be written to an internal register, or data read from the internal Status Register. When C/D=1, the data on the 8-bit data bus (DB0~DB7) are related to the Display Data Memory. They are the data to be written to or read from the Display Data Memory.
73
C/D
Input
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
Pin number
SYMBOL
I/O
DESCRIPTION For the SBN1661G_M18, pin 74 is the OSC1 pin of the on-chip RC oscillator. It is the input pin to the oscillator. An external resistor should be connected across the OSC1 and the OSC2. For the SBN1661G_M02, pin 74 is the CS pin. Usually, a signal decoded from the host microcontroller address lines or a port line (C51) is connected to this pin.
OSC1 74 CS OSC2 75 CL
Input
Output Input
For the SBN1661G_M18, pin 75 is the OSC2 pin. It is the output pin of the on-chip RC oscillator. For the SBN1661G_M02, pin 75 is the CL pin. Clock from master or an external clock source should be added to this pin. Enable signal (E) for the 68-type microcontroller, or READ (RD) signal for the 80-type microcontroller. If a 68-type microcotroller is selected as the host microcontroller, this pin should be connected to the ENABLE output of the microcontroller. A HIGH level on this pin indicates that the microcontroller intends to select the SBN1661G_X series. If a 80-type microcontroller is selected as the host microcontroller, this pin should be connected to the RD output of the microcontroller. A LOW level on this pin indicates that the microcontroller intends to read from the SBN1661G_X series.. Read/Write (R/W) signal for the 68-type microcontroller, or WRITE(WR) signal for the 80-type microcontroller. If a 68-type microcotroller is selected as the host microcontroller, this pin should be connected to the R/W output of the microcontroller. A HIGH level on this pin indicates that the microcontroller intends to read from the SBN1661G_X series. A LOW level on this pin indicates that the microcontroller intends to write to the SBN1661G_X series. If a 80-type microcontroller is selected as the host microcontroller, this pin should be connected to the WR output of the microcontroller. A LOW level on this pin indicates that the microcontroller intends to write to the SBN1661G_X series.
76
E/(RD)
Input
77
R/W(WR)
Input
78 79~86
VSS DB0~DB7 I/O
Ground pin. Bi-direction, tri-state 8-bit parallel data bus for interface with a host microcontroller. This data bus is for data transfer between the host microcontroller and the SBN1661G_X. Power supply for logic part of the chip.
87
VDD
Input The VDD should be in the range from 2.7 volts to 5.5 volts.
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
Pin number
SYMBOL
I/O
DESCRIPTION Hardware RESET and interface type selection. This pin is a dual function pin. It can be used to reset the SBN1661G_X and select the type of interface timing. The hardware RESET is edge-sensitive. It is not level-sensitive. That is, either a falling edge or a rising edge on this pin can reset the chip. The voltage level after the reset pulse selects the type of interface timing. If the voltage level after the reset pulse stays at HIGH, interface timing for the 68-type microcontroller is selected. If the voltage level after the reset pulse stays at LOW, then interface timing for the 80-type microcontroller is selected. Therefore, a positive RESET pulse selects the 80-type microcontroller for interface and a negative RESET pulse selects the 68-type microcontroller for interface.
88
RESET/IF
Input
The following diagram illustrates the reset pulse and the selected type of microcontroller.
Interface timing for the 80-type microcontroller is selected. Positive RESET pulse
Negative RESET pulse
Interface timing for the 68-type microcontroller is selected.
Fig.8 RESET pulse interface timing selection Frame output or input. The frame signal is the AC siganl for generating alternating bias voltage of reverse polarities for LCD cell. When the chip is used as Master in a Master-Slave connection, this pin is an output pin and sends frame signal to the slave. When the chip is used as Slave, this pin is an input pin and accepts frame signal from the master. External LCD Bias voltage. V5, V3, V2, V4, V1 Input The condition VDDV1V2V3V4V5 must always be met. In addition, VLCD (V5-VDD) should not exceed -13 volts. Selection for Master or Slave in a master-slave conneciton. When this pin is connected to VDD (hardwired-connection), the chip is used as Master. When this pin is connected to VSS, the chip is used as Slave. 93 M/S Input M/S VDD VSS FR Output Input COM0-COM15 output COM0-COM15 COM31-COM16 OSC1 Input NC OSC2 Output Input
89
FR
I/O
90, 91, 92, 94, 95
* The common scanning order for the slave driver is reverse to that for master.
2006 Aug 16
15 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
4
A SBN1661G_X-BASED DISPLAY SYSTEM
A SBN1661G_X-based display system is shown in Fig. 9. The SBN1661G_X , on the one side, interfaces with a host microcontroller via address bus , data bus, and control bus. The address bus from the microcontroller needs to be further decoded to generate Chip Select signal. The host microcontroller can perform READ/WRITE operation to the on-chip Display Data Memory, can send commands to the SBN1661G_X, and can program the internal registers to congifure the SBN1661G_X. How data is to be displayed on the LCD panel is completely controlled by the host microcontroller. On the other side, the SBN1661G_X provides 15 COMMON drivers and 61 SEGMENT drivers to drive the LCD panel. To expand the COMMON number and SEGMENT number, both the SBN1661G_M18 and SBN1661G_M02 can be used either as a master or as a slave in a master-slave connection. The synchronization between the master and the slave is via the FR (frame) signal and the CL (clock) signal supplied from the master to the slave. If only segment number needs to be expanded, then the SBN0080G_S18 or the SBN0080G_S02 can be used as slave.
Address bus Data bus Host microcontroller Control bus
Decoder
SBN1661G_X (master)
COM0 COM15
68-series 80-seris C51-series
Display Data Memory Registers
SEG1 SEG61
LCD Panel
SBN1661G_X (slave) COM15 Display Data Memory Registers
LCD Bias Power Supply
COM0
SEG1 SEG61
RESET
Fig.9 A SBN1661G_X series-based display system
2006 Aug 16
16 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
5 5.1
INTERFACE WITH A HOST MICROCONTROLLER Selection of interface type by use of the RESET/IF pin(pad)
The SBN1661G_X series can accept two types of interface timing for two types of microconftroller: the 68-type micrcontrollers and the 80-type microcontrollers. Selection of interface type is by use of the dual-function RESET/IF pin(pad). If the voltage at the RESET/IF pin(pad) stays at HIGH after RESET pulse, then the 68-type interface timing is selected. If the voltage at the RESET/IF pin(pad) stays at LOW after RESET pulse, then the 80-type interface timing is selected. The RESET of the SBN1661G_X is edge-sensitive, instead of level-sensitive. That is, a pulse on the RESET/IF input triggers reset only on the rising edge and falling edge of the pulse. The voltage level after the RESET pulse is used to select interface type. 5.2 Interface signal and operation
The interface signal between the host microcontroller and the SBN1661G_X are data bus and control bus. The data bus is an 8-bit (DB0~DB7) bi-directional bus. The control bus is composed of the following siganls: C/D, E/(RD), and R/W(WR). By means of data bus and control bus, the host microcontroller can write data to the on-chip Display Data Memory, can read data from the Display Data Memory, can program the internal registers, can send commands, and can read status of the chip. It is the host microcontroller's responsibility to put proper data and timing on the data bus and control bus to ensure proper communication. Table 8 lists the setting for control bus and the types of interface operation. Table 8 Interface signal and microcontroller operation 68-type interface R/W 1 0 1 0 80-type interface Operation RD 0 1 0 1 WR 1 0 1 0 The host microcontroller reads data from the Display Data Memory. The host microcontroller writes data to the Display Data Memory The host microcontroller reads the Status Register. The host microcontroller issues a command or writes data to an internal register.
COMMAN /DATA C/D 1 1 0 0 5.3
Interface Timing
Please refer to Fig. 22 and Fig. 24 for interface timing diagram and Table 42 , Table 43, Table 44, and Table 45 for AC characteristics of interface timing. 5.4 Interface Circuit
Please refer to Fig. 24, Fig. 25, and Fig. 26 for interface circuit examples.
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
6
DISPLAY DATA MEMORY AND LCD DISPLAY
The Display Data Memory is a static memory bit(cell) array of 32-row x 80-column. So, the total bit number of the Display Data Memory is 32 x 80 = 2560 bits. Each bit of the memory is mapped to a single pixel (dot) on the LCD panel. A "1" stored in the Display Data Memory bit corresponds to an ON pixel (black dot in normal display) of the LCD panel. A "0" stored in the Display Data Memory bit corresponds to an OFF pixel (background dot in normal display) of the LCD panel. Column outputs(Column 0~79) of the Display Data Memory is mapped to SEG 0~79 outputs of the SBN1661G_X. The mapping can be normal mapping or inverse mapping. Normal mapping means that Column0 is mapped to SEG0, Column1 to SEG1, Column2 to SEG2, and so on. Inverse mapping means that Column0 is mapped to SEG79, Column1 to SEG78, Column2 to SEG77, and so on. The mapping relation is decided by the Column/Segment Mapping Register. Any row (80 bits) of the Display Data Memory can be selected as the first row (COM0) to be displayed on the LCD panel. This is decided by the Display Start Line Register. The Display Start Line Register points at the first row of a block of the Display Data Memory, which will be mapped to COM0 of the LCD display. The length of the block of the memory can be 32 rows or 16 rows, which is decided by the Duty Select Register.
Column 77
Column 78
Column 79
Column 0
Column 1
Column 2
SEG 77
SEG 78
Row 0 Row 1 Row 2 Row 3
COM 0 COM 1 COM 2 COM 3
Row 28 Row 29 Row 30 Row 31
COM 15
LCD panel pixel array Display Data Memory Cell Array
Fig.10 Memory cell array and LCD pixel array
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data sheet (v6.3)
SEG 79
SEG 0
SEG 1
SEG 2
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7 7.1
DISPLAY CONTROL INSTRUCTIONS AND REGISTERS Registers and their states after hardware RESET
The SBN1661G_X has a set of registers. To ensure proper operation of the devices, these registers must be programmed with proper values after hardware reset. The registers and their states after RESET is given in Table 9. Table 9 Registers and their states after RESET Register Name Description The Display ON/OFF Register is a 1-bit register. After RESET, 0 its value is LOW and, therefore, the LCD display is turned OFF. The Display Start Line Register is a 6-bit register. After RESET, its value is 0 0000 and Row0 of the Display Data Memory is mapped to COM0. The Page Address Register is a 2-bit register. After RESET, its value is 11 and, therefore, it points to Page 3 of the Display Data Memory. The Column Address Register is a 7-bit register. After RESET, its value is 000 0000 and, therefore, it points to column 0 of the Display Data Memory. The Static Drive ON/OFF Register is a 1-bit register. After RESET, its value is LOW and static display is turned OFF. The Duty Select Register is a 1-bit register. After RESET, its value is HIGH and 1/32 display duty is selected. The Column/Segment Mapping Register is a 1-bit register. After RESET, its value is LOW and normal mapping is selected. The Status Register shows the current state of the SBN1661G_X. It is a 4-bit register, with each bit showing the status of a programmed function. 00 0000 States after RESET
Display ON/OFF Register
Display Start Line Register
Page Addres Register
11
Column Address Register
000 0000
Static Drive ON/OFF Register Duty Select Register Column/Segment Mapping Register Status Register
0 1 0
0000 0000
7.2
Display ON/OFF and the Display ON/OFF Register
The Display ON/OFF Register is a 1-bit Register. When this bit is progammed to HIGH, the display is turned ON. When this bit is programmed to LOW, the display is turned OFF. When display is turned OFF, SEG0~SEG60 will stay at either V2 or V3, and COM0~COM15 will stay at their previous value before the Display OFF command is issued. To program this register, the setting of control bus is given in Table 10 and the setting of the data bus is given in Table 11. Table 10 Setting of the control bus for programming the Display ON/OFF Register C/D 0 E/(RD) 1 R/W(WR) 0
Table 11 Setting of the data bus for programming the Display ON/OFF Register D7(MSB) 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0(LSB) D0
When D0=1, the code is AF(Hex) and the display is turned ON. When D0=0, the code is AE(Hex) and the display is turned OFF.
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7.3
Display Start Line and the Display Start Line Register
The Display Start Line Register is a 5-bit Register. It points at the first row of a block of the Display Data Memory, which will be mapped to COM0. The length of the block of the memory can be 32 rows or 16 rows, which is decided by the Duty Select Register. For example, if the Display Start Line Register is programmed with 00010 ( decimal 2) and display duty is 1/32, then Row2 of the Display Data Memory will be mapped to COM0 of LCD panel, Row3 to COM1, Row4 to COM2, Row30 to COM28, Row31 to COM29, Row0 to COM30, and finally Row1 to COM31, as illustrated in Fig. 11. However, in this case, only Row2~Row17 can be displayed on COM0~COM15, as COM16~COM31 are not availabe from the chip.
SEG 77
SEG 78
Column 77
Column 78
Column 79
COM 0 COM 1 COM 2 COM 3
Column 0
Column 1
Row 0 Row 1 Row 2 Row 3 COM 28 0 0 0 1 0 COM 29 COM 30 COM 31 Row 28 Row 29 Row 30 Row 31
A4 A3 A2 A1 A0 Display Start Line Register
Column 2
LCD panel
Display Data Memory Fig.11 Display Start Line Register To program this register, the setting of the control bus is given in Table 12 and the setting of the data bus is given in Table 13. Table 12 The setting of the control bus for programming the Display Start Line Register C/D 0 E/(RD) 1 R/W(WR) 0
Table 13 The setting of the data bus for programming the Display Start Line Register D7(MSB) 1 D6 1 D5 0 D4 A4 D3 A3 D2 A2 D1 A1 D0(LSB) A0
A4, A3, A2, A1, and A0 are Start Line address bits and they can be programmed with a value in the range from 0 to 31. Therefore, the code can be from 1100 0000 (C0 Hex) to 1101 1111 (DF Hex).
2006 Aug 16
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data sheet (v6.3)
SEG 79
SEG 0
SEG 1
SEG 2
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7.4
Display Data Memory Page and the Page Address Register
The on-chip Display Data Memory is divided into 4 pages: Page 0, Page 1, Page 2, and Page 3, with each page having 80 bytes in horizontal direction. Page 0 is from Row 0 to Row 7, Page 1 from Row 8 to Row 15, Page 2 from Row 16 to Row 23, and Page 3 from Row 24 to Row 31, as shown in Fig 12. When the host microtroller intends to perform a READ/WRITE operation to the Display Data Memory, it has to program the Page Adrress Register to indicate which page it intends to access.
Column 78(Byte78)
Page 0
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Page 1
Page 2
Page 3
Row0 Row1 Row2 Row3 Row4 Row5 Row6 Row7 Row8 Row9 Row10 Row11 Row12 Row13 Row14 Row15 Row16 Row17 Row18 Row19 Row20 Row21 Row22 Row23 Row24 Row25 Row26 Row27 Row28 Row29 Row30 Row31
Fig.12 Page/Column allocation of the Display Data Memory To program this register, the setting of the control bus is given in Table 14 and the setting of the data bus is given in Table 15. Table 14 The setting of the control bus for programming the Page Address Register C/D 0 E/(RD) 1 R/W(WR) 0
Table 15 The setting of the data bus for programming the Page Address Register D7(MSB) 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 A1 D0(LSB) A0
A1and A0 are page address bits and can be programmed with a value in the range from 0 to 3. A1A0=00 selects Page 0, A1A0=01 selects Page 1, A1A0=10 selects Page 2, and A1A0=11 selects Page 3. Therefore, the code can be from 1011 1000 (B8 Hex) to 1011 1011 (BB Hex).
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Column 77(Byte77)
data sheet (v6.3)
Column 79(Byte79)
Column 0(Byte0)
Column 1(Byte1)
Column 2(Byte2)
Column 3(Byte3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7.5
Column address and the Column Address Register
The Column Address Register points at a column of the Display Data Memory which the host microcontroller intends to perform a READ/WRITE operation. The Column Address Register automatically increments by 1 after a READ or WRITE operation is finished. When the Column Address Register reaches 79, it overflows to 0. Please refer to Fig.12 for the column sequence in a page of the Display Data Memory. To program this register, the setting of the control bus is given in Table 16 and the setting of the data bus is given in Table 17. Table 16 The setting of the control bus for programming the Column Address Register C/D 0 E/(RD) 1 R/W(WR) 0
Table 17 The setting of the data bus for programming the Column Address Register D7(MSB) 0 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0(LSB) A0
A6~A0 are column address bits and can be programmed with a value in the range from 0 to 79. Therefore, the code can be from 0000 0000 (00 Hex) to 0100 1111 (4F Hex).
2006 Aug 16
22 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7.6
Mapping between Memory Cloumns and Segments and the Column/Segment Mapping Register
The Column/Segment Mapping Register is a 1-bit register and selects the mapping relation between the column outputs of the Display Data Memory and the Segment outputs SEG0~SEG79. If this register is programmed with HIGH, then the data from column 79 of the Display Data Memory will be output from SEG0. This type of mapping is called inverted mapping. If this register is programmed with LOW, then data from column 0 of the Display Data Memory will be output from SEG0. This type of mapping is called normal mapping. By use of this register, the flexibility of component placement and routing on a PCB can be increased.
Segment Driver
SEG 77 SEG 78 SEG 79 SEG 0 SEG 1 SEG 2
Segment Driver
SEG 77 SEG 78 Column 78 SEG 79 Column 79 SEG 0 SEG 1 SEG 2
Normal Mapping (D=0)
Column 77 Column 78 Column 79 Column 0 Column 1 Column 2 Row 0 Row 1 Row 2 Row 3
Inverted mapping (D=1)
Row 0 Row 1 Row 2 Row 3 Column 77 Column 0 Column 1 Column 2
Row 28 Row 29 Row 30 Row 31
Row 28 Row 29 Row 30 Row 31
Display Data Memory
Display Data Memory
Fig.13 Column/Segment Mapping Register. To program this register, the setting of the control bus is given in Table 18 and the setting of the data bus is given in Table 19. Table 18 The setting of the control bus for programming the Column/Segment Mapping Register C/D 0 E/(RD) 1 R/W(WR) 0
Table 19 The setting of the data bus for programming the Memory/Segment Mapping Register D7(MSB) 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0(LSB) D
The least significant bit D can be programmed with either 0 or 1. Therefore, the codes are A0 Hex or A1 Hex.
2006 Aug 16
23 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7.7
Static Drive ON/OFF and the Static Drive ON/OFF register
The Static Drive ON/OFF Register is a 1-bit register. It is used to turn ON or OFF the Static Drive Mode of the SBN1661G_X. When this register is programmed with HIGH, Static Drive Mode is turned ON and the device enters into Static Drive Mode, in which the internal clock circuitry is disabled and the switching of the internal logic is suspended. When this register is programmed with LOW, Static Drive Mode is turned OFF and the chip returns to normal operation. This register is used in combination with the Display ON/OFF register to make the current consumption of the LCD module reduced to almost static level. By turning OFF the display and turning ON the static drive mode,the chip is configured into the following state: * all COMMON and SEGMENT outputs are set to VDD, * on-chip oscillator or external clock is inhibited and internal logic circuit stays idle, * OSC2 is in floating state (please refer to Section 11 , On-chip RC Oscillator), and * the state of registers and the data of the Display Data Memory are kept unchanged. In addition to turning ON the static drive mode and turning OFF the display, to really reduce the power consumption of the LCD module, the host microcontroller should also send out a power-save signal to turn off the PNP transistor in the bias circuit, such that the current flow from VDD to VEE can be cut off, as shown in Fig. 14.
VDD
VDD
VDD
V0
V0 V1 V2 V3 V4 V5
C C C C Microcontroller C
V1 V2 V3 V4 V5
SEG0~SEG60
COM0~COM15
VSS
Power Save Signal
VEE
Fig.14 Power Save Mode
To program this register, the setting of the control bus is given in Table 20 and the setting of the data bus is given in Table 21. Table 20 The setting of the control bus for programming the Static Drive ON/OFF Register C/D 0 E/(RD) 1 R/W(WR) 0
Table 21 The setting of the data bus for programming the Static Drive ON/OFF Register D7(MSB) 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0(LSB) D
The least significant bit D0 can be programmed with either 0 or 1. Therefore, the code is A4 Hex or A5 Hex.
2006 Aug 16
24 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7.8
Select Duty and the Select Duty Register
The Select Duty Register is a 1-bit register. If it is programmed with HIGH, 1/32 display duty is selected. If it is programmed with LOW, 1/16 display duty is selected. To program this register, the setting of the control bus is given in Table 22 and the setting of the data bus is given in Table 23. Table 22 The setting of the control bus for programming the Select Duty Register C/D 0 E/(RD) 1 R/W(WR) 0
Table 23 The setting of the data bus for programming the Select Duty Register D7(MSB) 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0(LSB) D
The least significant bit D can be programmed with either 0 or 1. Therefore, the code is A8 Hex or A9 Hex. In a Master-Slave connection using the SBN1661G_M18 or the SBN1661G_M02 as the master, COM0~COM15 will be from the master and COM16~COM31 will be from the slave. The Select Duty Register of both the Master and the Slave should be programmed with HIGH to select 1/32 duty. Fig.15 shows the COMMON sequence of this connection.
Frame Signal (From Master)
COM0~COM15 (From Master) COM16~COM31 (From Slave)
0
1
2
13 14 15
0
1
2
13 14 15
16 17 18
29 30 31
16 17 18
29 30 31
Fig.15 COMMON sequence of Master-Slave connection This register is not available in the SBN0080G_S18 and the SBN0080G_S02, because both the devices are purely Segment Drivers and their duty cycle is decided by the FR and the CL from the master.
2006 Aug 16
25 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
7.9
Status Read and Status Register
The Status Register shows the current state of the SBN1661G_X. It can be read by the host microcontroller. Bit 7~4 shows the status and Bit 3~0 are always fixed at 0. To read the Status Register, the setting of the control bus is given in Table 24, the bit allocation is given in Table 25 and the description for each bit is given in Table 26. Table 24 The setting of the control bus for reading the Status Register C/D 0 E/(RD) 0 R/W(WR) 1
Table 25 The Status Register bit allocation D7(MSB) BUSY D6 MAPPING D5 ON/OFF D4 RESET D3 0 D2 0 D1 0 D0(LSB) 0
Table 26 The Status Register bit description Bit BUSY Description BUSY=1 indicates that the SBN1661G_X is currently busy and can not accept new command or data. The SBN1661G_X is executing a command or is in the process of reset. BUSY=0 indicates that the SBN1661G_X is not busy and is ready to accept new command or data. MAPPING MAPPING=1 indicates that the Column/Segment Mapping Register has been programmed with a value of "1" and the SEG0 is mapped to Column 79 of the Display Data Memory (inverted mapping). MAPPING=0 indicates that the Column/Segment Mapping Register has been programmed with a value of "0" and the SEG0 is mapped to Column 0 of the Display Data Memory (normal mapping). ON/OFF The ON/OFF bit indicates the current of status of display. If ON/OFF=0, then the display has been turned ON. If ON/OFF=1, then the display has been turned OFF. Note that the polarity of this bit is inverse to that of the Display ON/OFF Register. RESET RESET=1 indicates that the SBN1661G_X is currently in the process of being reset. RESET=0 indicates that the SBN1661G_X is currently in normal operation.
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
8
COMMANDS
The host microcontroller can issue commands to the SBN1661G_X. Table 27 lists all the commands. When issuing a command, the host microcontroller should put the command code on the data bus. The host microcontroller should also give the control bus C/D, E(RD), and R/W(WR) proper value and timing. Table 27 Commands COMMAND CODE COMMAND D7 Write Display Data Read Display Data Read-Modify-Write END Software Reset 8.1 D6 D5 D4 D3 D2 D1 D0 Write a byte of data to the Display Data Memory. Read a byte of data from the Display Data Memory. 0 0 0 Start Read-Modify-Write operation. Stop Read-Modify-Write operation. Software Reset. Data to be written into the Display Data Memory. Data read from the Display Data Memory. 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 1 FUNCTION
Write Display Data
The Write Display Data command writes a byte (8 bits) of data to the Display Data Memory. Data is put on the data bus by the host microcontroller. The location which accepts this byte of data is pointed to by the Page Address Register and the Column Address Register. At the end of the command operation, the content of the Column Address Register is automatically incremented by 1. For page address and column address of the Display Data Memory, please refer to Fig. 12. Table 28 gives the control bus setting for this command. Table 28 The setting of the control bus for issuing Write Display Data command C/D 1 E/(RD) 1 R/W(WR) 0
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
8.2
Read Display Data
The Read Display Data command starts a 3-step operation. 1. First, the current data of the internal 8-bit output latch of the Display Data Memory is read by the microcontroller, via the 8-bit data bus DB0~DB7. 2. Then, a byte of data of the Display Data Memory is transferred to the 8-bit output latch from a location specified by the Page Address Register and the Column Address Register, 3. Finally, the content of the Column Address Register is automatically incremented by one. Fig. 16 shows the internal 8-bit ouptut latch located between the 8-bit I/O data bus and the Display Data Memory cell array. Because of this internal 8-bit output latch, a dummy read is needed to obtain correct data from the Display Data Memory. For Display Data Write operation, a dummy write is not needed, because data can be directly written from the data bus to internal memory cells.
(8-bit bi-directional data bus)
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Write Display Data Read Display Data
8-bit output latch
Row Address Decoder
Display Data Memory cell array ( 32 row x 80 column )
Column Address Decoder
Fig.16 Read Display Data Memory
Table 29 gives the control bus setting for this command. Table 29 The setting of the control bus for issuing Read Display Data command C/D 1 E/(RD) 0 R/W(WR) 1
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
8.3
Read-Modify-Write
When the Read-Modify-Write command is issued, the SBN1661G_X enters into Read-Modify-Write mode. In normal operation, when a Read Display Data command or a Write Display Data command is issued, the content of the Column Address Register is automatically incremented by one after the command operation is finished. However, during Read-Modify-Write mode, the content of the Column Address Register is not incremented by one after a Read Display Data command is finished; only the Write Display Data command can make the content of the Column Address Register automatically incremented by one after the command operation is finished. During Read-Modify-Write mode, any other registers, except the Column Address Register, can be modified. This command is useful when a block of the Display Data Memory needs to be repeatedly read and updated. Fig. 17 gives the change sequence of the Column Address Register during Read-Modify-Write mode. Figure 18 gives the flow chart for Read-Modify-Write command.
Read-Modify-Write command issued.
END command issued.
Read-Modify-Write duration Column Address N N+1 N+2 N+3 N+m N
Internal Buffer Register
Re-load column address by issuing the END command
Fig.17 Column address change during Read-Modify-Write
2006 Aug 16
29 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
Set Page Address Register
Set Column Address Register
Read-Modify-Write command
Dummy Read
Read Display Data Memory
Write Display Data Memory
Finish Modifying ? Yes
No
END Fig.18 The flowchart for Read-Modify-Write Table 30 gives the setting for the control bus and the setting of the data bus is given in Table 31. Table 30 The setting of the control bus for the Read-Modify-Write command C/D 0 E/(RD) 1 R/W(WR) 0
Table 31 The setting of the data bus for the Read-Modify-Write command D7(MSB) 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0(LSB) 0
The command code is E0 Hex. 8.4 The END command
The END command releases the Read-Modify-Write mode and re-loads the Column Address Register with the value previously stored in the internal buffer (refer to Fig. 17) when the Read-Modify-Write command was issued. Table 32 gives the setting for the control bus and the setting of the data bus is given in Table 33.
2006 Aug 16
30 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
Table 32 The setting of the control bus for the END command C/D 0 E/(RD) 1 R/W(WR) 0
Table 33 The setting of the data bus for the END command D7(MSB) 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0(LSB) 0
The command code is EE Hex. 8.5 Software RESET command
The Software Reset command is different from the hardware reset and can not be used to replace hardware reset. When Software Reset is issued by the host microcontroller, * the content of the Display Start Line Register is cleared to zero(A4~A0=00000), * the Page Address Register is set to 3 (A1 A0 = 11), * the content of the Display Data Memory remains unchanged, and * the content of all other registers remains unchanged. Table 34 gives the setting for the control bus and the setting of the data bus is given in Table 35. Table 34 The setting of the control bus for Software RESET C/D 0 E/(RD) 1 R/W(WR) 0
Table 35 The setting of the data bus for Software RESET D7(MSB) 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0(LSB) 0
The command code is E2 Hex.
2006 Aug 16
31 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
9
LCD BIAS CIRCUIT
A typical LCD bias circuit is shownin Fig. 19. The condition VDD V1 V2 V3 V4 V5 must always be met. The maximum allowed voltage for LCD bias (VLCD=VDD-V5) should not exceed 13 volts.
COMPONENT
RECOMMENDED VALUE 0.1 F, electrolytic 2.2K 7.5K 10K PNP
C C C C Microcontroller C R1 R1 R2 R1 R1 VDD V1 V2 V3 V4 V5 R3
Power Save Signal
C R1 R2 R3 TR1
VDD
VDD VDD
VDD V1 V2 V3 V4 V5
SEG0~SEG60
COM0~COM15
VSS
TR1
VEE
Fig.19 LCD Bias circuit
2006 Aug 16
32 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
10 COMMON, SEGMENT OUTPUT VOLTAGE The output voltage level of COMMON driver and SEGMENT driver is given in Table 36. The output voltage level of COMMON driver is decided by the combination of Frame signal, internal COMMON COUNTER output, and the Display ON/OFF register. The output voltage level of SEGMENT driver is decided by the combination of Frame signal, Display Data, and the Display ON/OFF register. Table 36 COMMON/SEGMENT ouptut voltage level FR L L H H x(don't care) Data L H L H x(don't care) DISPLAY ON/OFF ON ON ON ON OFF SEG0~SEG60 (SEG0~SEG79) V3 V5 V2 VDD V2 or V3 COM0~COM15 V4 VDD V1 V5 previous voltage
Note that, in the above table, "Data" for the COM0~COM15 is actually the output of the internal COMMON COUNTER, which generates horizontal raster scanning signal. During RESET, both SEGMENT and COMMON outputs are at VDD.
2006 Aug 16
33 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
11 ON-CHIP RC OSCILLATOR The SBN1661G_M18 has an on-chip RC-type oscillator. All other three members of the family do not have on-chip oscillator and need external clock source. The output CLK of the oscillator is the basic timing clock of the internal control logic, display pixel rate, and is also used to generate frame signal. The capacitor of the RC-oscillator is fabricated on-chip. Only an external resistor Rf needs to be connected across OSC1 and OSC2. The recommended value of Rf is in the range from 1000K ohm to 1200K ohm. During PCB layout, this resistor should be placed as close to the SBN1661G_M18 as possible, such that stray capacitance, inductance, and resistance can be minimized.
VDD
CLK
VDD
OSC1
OSC2
Disable
Disable
Disable
VSS
VSS
Rf
1.0 M(typical) Fig.20 On-chip RC oscillator
The characteristics of the oscillator is given is Table. 37. Table 37 On-chip RC oscillator characteristics, Tamb = -20 to +75 C Oscillation Oscillation frequency at VDD=5V, Rf= 1.0 M 20% Oscillation frequency at VDD=3V, Rf= 1.0 M 20% min. 17.6 15.7 typ. 21.5 19.1 max. 25.9 22.8 unit KHz KHz
2006 Aug 16
34 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
12 ELECTRICAL CHARACTERISTICS 12.1 Absolute maximum rating
Table 38 Absolute maximum rating SYMBOL VDD VLCD (note 2) VI PD Tstg Tamb Tsol (note 3) Notes 1. The following applies to the Absolute Maximum Rating: a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. b) The SBN1661G_X series includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge (ESD). However, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) Parameters are valid over operating temperature range unless otherwise specified. d) All voltages are with respect to VSS, unless otherwise noted. 2. The condition VDD V1 V2 V3 V4 V5 must always be met. 3. QFP-type packages are sensitive to moisture of the enviroment, please check the drypack indicator on the tray package before soldering. Exposure to moisture longer than the rated drypack level may lead to cracking of the plastic package or broken bonding wiring inside the chip. PARAMETER voltage on the VDD pin(pad) LCD bias voltage, VLCD=VDD-V5 input voltage on any pin with respect to VSS power dissipation storage temperature range operating ambient temperature range soldering temperature/time at pin -55 -40 -0.3 MIN. -0.3 MAX. +7.0 13 VDD + 0.3 250 +125 + 85 260 C, 10 Second UNIT Volts Volts Volts mW C C
2006 Aug 16
35 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
13 DC CHARACTERISTICS Table 39 DC Characteristics VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS, unless otherwise specified; Tamb = -20 to +75 C. SYMBOL VDD VLCD VIL VIH VOL VOH ISTBY IDD(1) IDD(2) IDD(3) IDD(4) fosc(VDD=5V), fosc(VDD=3V) Cin RON tR Notes: 1. Conditions for the measurement: OSC1=OSC2=VDD, measured at the VDD pin. 2. These values are measured when the microcontroller does not perform any READ/WRITE operation to the chip. 3. These meaurements are for different members of the series: a) IDD(1) are measured for the SBN1661G_M02 and the SBN0080G_S02, b) IDD(2) are measured for the SBN1661G_M18, and c) IDD(3) are measured for the SBN0080G_S18. 4. These values are measured when the microcontroller continuously performs READ/WRITE operation to the chip. 5. This measurement is for the transmission high-voltage PMOS or NMOS of COM0~15 and SEG0~60(79). Please refer to Section 18 for these driver circuit. The meaurement is for the case when the voltage differential between the source and the drain of the high voltage PMOS or NMOS is 0.1 volts. 6. The value is relative to the RESET pulse edge. That is, 1.0 S after the last RESET edge, the device is completely reset. PARAMETER Supply voltage for logic LCD bias voltage VLCD= VDD-V5 LOW level input voltage HIGH level input voltage LOW level output voltage HIGH level output voltage Standby current at V5=-5 volts Operating current at V5=-5 volts and fCL=2KHz, VLCD=10 volts Operating current at V5=-5 volts and Rf=1 M, VLCD=10 volts Operating current at V5=-5 volts and fCL=21.8 KHz, VLCD=10 volts Operating current at V5=-5 volts and tCYC=100 KHz, VLCD=10 volts Note 4 Note 2 & Note 3 For all inputs For all inputs For all outputs For all outputs Note 1 2.7 12.3 5.3 21.7 0 VDD-1.2 0.0 VDD - 0.3 CONDITIONS MIN. 4.5 TYP. 5.0 MAX. 5.5 13 0.8 VDD 0.3 VDD 3.0 5.6 15.6 10.8 26.2 UNIT V V V V V V A A A A A
Please refer to Table 37, On-chip RC oscillator characteristics. Input capacitance of all input pins LCD driver ON resistance Reset time Note 5 Note 6 1.0 5.0 5.0 8.0 7.5 pF K S
2006 Aug 16
36 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
14 AC TIMING CHARACTERISTICS 14.1 CL and FR timing
TF TWHCL
TR
0.9 x VDD
CL
TWLCL
0.1 x VDD
0.9 x VDD 0.1 x VDD
0.9 x VDD 0.1 x VDD
0.1 x VDD
TDFR
FR
0.1 x VDD
Fig.21 Display Control Signal Timing Table 40 CL and FR timing characteristics at VDD=5 volts VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = -20 to +75 C. SYMBOL TWHCL TWLCL TR TF TDFR(input) TDFR(output) PARAMETER CL clock high pulse width CL cock low pulse width CL clock rise time CL clock fall time FR delay time (input) When used as input in Slave Mode application When used as output in Master Mode application, with CL= 100 pF. -2.0 CONDITIONS MIN. 33 33 28 28 0.2 120 120 1.6 TYP. MAX. UNIT s s ns ns S S
FR delay time (output)
0.2
0.36
Table 41 CL and FR timing characteristics at VDD=3 volts VDD = 3 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = -20 to +75 C. SYMBOL TWHCL TWLCL TR TF TDFR(input) TDFR(output) PARAMETER CL clock high pulse width CL cock low pulse width CL clock rise time CL clock fall time FR delay time (input) When used as input in Slave Mode application When used as output in Master Mode application, with CL= 100 pF. -3.6 CONDITIONS MIN. 65 65 50 50 0.36 220 220 3.6 TYP. MAX. UNIT s s ns ns S S
FR delay time (output)
0.32
0.6
2006 Aug 16
37 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
14.2
AC timing for interface with an 80-type microcontroller
C/D, CS
0.9 x VDD 0.1 x VDD
0.9 x VDD 0.1 x VDD
tAS tF tRWPW RD, WR
0.9 x VDD 0.1 x VDD 0.1 x VDD
tAH tR
0.9 x VDD
tCYC tDS D0 to D7 (WRITE) D0 to D7 (READ)
Hi-Z
0.9 x VDD 0.1 x VDD
tDH
0.9 x VDD 0.1 x VDD
Hi-Z
Hi-Z
0.9 x VDD 0.1 x VDD
0.9 x VDD 0.1 x VDD
Hi-Z
tACC
tOH
Fig.22 AC timing for interface with a 80-type microcontroller
Table 42 AC timing for interface with a 80-type microcontorller at VDD=5 volts VDD = 5 V 10%; VSS = 0 V; Tamb = -20 C to +75C. symbol tAS tAH tF, tR tRWPW tCYC tDS tDH tACC tOH parameter Address set-up time Address hold time Read/Write pulse falling/rising time Read/Write pulse width System cycle time Data setup time Data hold time Data READ access time Data READ output hold time 10 200 1000 80 10 90 60 CL= 100 pF. Refer to Fig. 23. min. 20 10 15 max. test conditons unit ns ns ns ns ns ns ns ns ns
Table 43 AC timing for interface with an 80-type microcontorller at VDD=3 volts VDD = 3 V 10%; VSS = 0 V; Tamb = -20 C to +75C. symbol tAS tAH tF, tR tRWPW tCYC tDS parameter Address set-up time Address hold time Read/Write pulse falling/rising time Read/Write pulse width System cycle time Data setup time 400 2000 160 min. 40 20 15 max. test conditons unit ns ns ns ns ns ns
2006 Aug 16
38 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
symbol tDH tACC tOH Note:
parameter Data hold time Data READ access time Data READ output hold time
min. 20
max. 180
test conditons CL= 100 pF, Refer to 23.
unit ns ns ns
20
120
The measurement is with the load circuit connected. The load circuit is shown in Fig. 23.
Pin CL VSS
CL= 100 pF (including wiring and probe capacitance).
Fig.23 Load circuit.
2006 Aug 16
39 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
14.3
AC timing for interface with a 68-type microcontroller
tCYC tR E
0.9 x VDD 0.1 x VDD 0.1 x VDD
tF
0.9 x VDD
tEW
0.1 x VDD
tAS1 R/W
0.9 x VDD 0.1 x VDD
tAH1
0.9 x VDD 0.1 x VDD
tAS2 C/D, CS
0.9 x VDD 0.1 x VDD
tAH2
0.9 x VDD 0.1 x VDD
tDS D0 to D7 (WRITE)
Hi-Z
0.9 x VDD 0.1 x VDD
tDH
0.9 x VDD 0.1 x VDD
Hi-Z
tACC D0 to D7 (READ)
Hi-Z
0.9 x VDD 0.1 x VDD
tOH
0.9 x VDD 0.1 x VDD
Hi-Z
Fig.24 AC timing for interface with a 68-type microcontroller Table 44 AC timing for interface with a 68-type microcontroller at VDD=5 volts VDD = 5 V 10%; VSS = 0 V; Tamb = -20 C to +75C. symbol tAS1 tAS2 tAH1 tAH2 tF, tR tCYC tEWR tEWW tDS tDH tACC tOH parameter Address set-up time with respect to R/W Address set-up time with respect to C/D, CS Address hold time with respect to R/W Address hold time respect with to C/D, CS Enable (E) pulse falling/rising time System cycle time Enable pulse width for READ Enable pulse width for WRITE Data setup time Data hold time Data access time Data output hold time 10 1000 100 80 80 10 90 60 CL= 100 pF. Refer to Fig. 23. min. 20 20 10 10 15 Note 1 max. test conditons unit ns ns ns ns ns ns ns ns ns ns ns ns
2006 Aug 16
40 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
Table 45 AC timing for interface with a 68-type microcontroller at VDD=3 volts VDD = 3 V 10%; VSS = 0 V; Tamb = -20 C to +75C. symbol tAS1 tAS2 tAH1 tAH2 tF, tR tCYC tEWR tEWW tDS tDH tACC tOH Note: 1. The system cycle time(tCYC) is the time duration from the time when Chip Enable is enabled to the time when Chip Select is released. parameter Address set-up time with respect to R/W Address set-up time with respect to C/D, CS Address hold time with respect to R/W Address hold time respect with to C/D, CS Enable (E) pulse falling/rising time System cycle time Enable pulse width for READ Enable pulse width for WRITE Data setup time Data hold time Data access time Data output hold time 20 2000 200 160 160 20 180 120 CL= 100 pF. Refer to Fig. 23. 40 40 20 20 15 Note 1 min. max. test conditons ns ns ns ns ns ns ns ns ns ns ns ns unit
2006 Aug 16
41 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
15 MICROCONTROLLER INTERFACE CIRCUIT 15.1 Example for interface with a 80-family microcontroller
VDD
VDD A0 C/D
VDD
Note: This example is applicable to the SBN1661G_M02.
A1~A7 IORQ 80-family Microcontroller D0~D7 RD WR RES GND RESET Negative LCD bias voltage
DECODER
CS
SBN1661G_M02
DB0~DB7 RD WR RESET/IF VSS
V5
Fig.25 Interface example with an 80-family microcontroller
15.2
Example for interface with a 68-family microcontroller
VDD
VDD A0 C/D
VDD
Note: This example is applicable to the SBN1661G_M02. The CS selection for the SBN0080G_S18 and the SBN0080G_S02 can be decoded from the address lines in the same way. For application with the SBN1661G_M18, which does not have a CS input, the CS output from the decoder must be ORed with C/D, E, and R/W.
A1~A15 VMA 68-family Microcontroller D0~D7 E R/W RES GND RESET Negative LCD bias voltage
DECODER
CS
SBN1661G_M02
DB0~DB7 E R/W RESET/IF VSS
V5
Fig.26 Interface example with a 68-family microcontroller
2006 Aug 16
42 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
15.3
Example for interface with other types of 8-bit microcontroller
VDD
VDD
C/D
(indicating commad/data) C/D Address or I/O space decoding
VDD
Note: This example is applicable only to the SBN1661G_M18, which does not have a CS input and the CS output from the address or I/O space decoding circut must be ORed with C/D, RD(E), and (WR)R/W.
Address
8-bit Microcontroller
D0~D7 E R/W RES GND
SBN1661G_M18
DB0~DB7 RD(E) WR(R/W) RESET/IF VSS
V5
RESET Negative LCD bias voltage
Fig.27 Interface example with an 8-bit microcontroller
2006 Aug 16
43 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
16 SYNCHRONIZATION OF CLOCK AND FRAME IN MASTER/SLAVE CONNECTIONS To expand COMMON/SEGMENT number, both the SBN1661G_M18 and the SBN1661G_M02 can be used Master. They can also be used as Slave. However, if the SBN1661G_M02 is used as Master, external clock source is needed, as it has no on-chip oscillator. In master/slave connections, clock and frame between the master and its slaves must be in synchronization. The SBN0080G_S18 and the SBN0080G_S02 can be used only as Slave for SEGMENT expansion. 16.1 SBN1661G_M18 connected with a SBN1661G_M18
To LCD SEGMENT
To LCD SEGMENT
SBN1661G_M18
VDD
To LCD COMMON
SBN1661G_M18
To LCD COMMON
M/S
Master M/S OSC1 OSC2 FR
VSS
Slave OSC1 OSC2 FR
Rf
Fig.28 SBN1661G_M18 connected with a SBN1661G_M18. 16.2 SBN1661G_M18 connected with more than two SBN0080G_S18
To LCD SEGMENT To LCD SEGMENT To LCD SEGMENT
VDD
SBN1661G_M18
To LCD COMMON
SBN0080G_S18
Slave FR CL FR
SBN0080G_S18
Slave CL FR
M/S
Master OSC1 OSC2
Rf
CMOS buffer
Note: when more than two slaves are connected, a CMOS clock buffer is needed to drive all the slaves. The duty and phase of the clock to all the slaves must be the same as that for the master.
Fig.29 SBN1661G_M18 connected with more than two SBN0080G_S18
2006 Aug 16
44 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
16.3
SBN1661G_M02 connected with a SBN1661G_M02
To LCD SEGMENT To LCD SEGMENT
SBN1661G_M02
VDD
To LCD COMMON
SBN1661G_M02
To LCD COMMON
M/S
Master M/S CL FR
VSS
Slave CL FR
External clock source
Fig.30 SBN1661G_M02 connected with a SBN1661G_M02.
16.4
SBN1661G_M02 connected with a SBN0080G_S02
To LCD SEGMENT To LCD SEGMENT
SBN1661G_M02
VDD
To LCD COMMON
SBN0080G_S02
Slave FR CL FR
M/S
Master CL
External clock source
Fig.31 SBN1661G_M02 connected with a SBN0080G_S02.
2006 Aug 16
45 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
17 TYPICAL APPLICATIONS 17.1 1/16 duty, 10 characters x 2 lines
COM0
In this application, 10-characters x 2-lines can be displayed, if the format of character font is 6 x 8 pixels.
16 x 61 LCD Panel
COM15 SEG0 SEG60
SEG0 COM15
SEG60
SBN1661G_M18
COM0
Fig.32 1/16 duty, 10 characters x 2 lines 17.2 1/16 duty, 23 characters x 2 rows
COM0
In this application, 23-characters x 2-lines can be displayed, if the format of character font is 6 x 8 pixels.
COM15
16 x 141 LCD Panel
SEG0 SEG60 SEG61 SEG140
SEG0 COM15
SEG60
SEG0
SEG79
FR
SBN1661G_M18
COM0
SBN0080G_S18
CL (slave)
(master)
Fig.33 1/16 duty, 23 characters x 2 lines 17.3 1/32 duty, 33 characters x 4 lines
COM0 COM15
32 x 202 LCD Panel
SEG0 SEG60 SEG61 SEG140
COM16 COM31 SEG141 SEG201
SEG0 COM15
SEG60
SEG0
SEG79
SEG0
SEG60 COM0
FR
FR
SBN1661G_M18
COM0
SBN0080G_S18
CL (slave) CL
SBN1661G_M18
(slave)
(master)
COM15
In this application, 33-characters x 4-lines can be displayed, if the format of character font is 6 x 8 pixels.
Fig.34 1/32 duty, 33 characters x 4 lines
2006 Aug 16
46 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
18 PIN CIRCUITS Table 46 MOS-level schematics of all input, output, and I/O pins. SYMBOL
Input/ output
VDD
CIRCUIT
NOTES
C/D, R/W(WR), E/RD, RESET/IF
Inputs
VSS
VDD
M/S
Input
VSS
VDD
CLK
VDD
OSC1
OSC2
OSC1, OSC2
Disable Disable Disable
The circuit encircled inside the red dashed frame is the oscillator circut.
VSS
VSS
VDD
Enable
VDD
Output Enable
D0~D7, FR
I/O
Data out
VSS
VSS
Data in
2006 Aug 16
47 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
SYMBOL
Input/ output
VDD
CIRCUIT
NOTES
EN1
VDD
VDD
V5 VDD
SEG0~79
EN2
V5
V2
SEG0~79
V3
V5 VDD
EN3
V5 VDD
EN4
V5
V5
VDD
EN1
VDD
VDD
V5 VDD
COM0~15
V5
EN2
V1
COM0~15
V4
V5 VDD
EN3
V5 VDD
EN4
V5
V5
2006 Aug 16
48 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
19 APPLICATION NOTES 1. It is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. As the ICs are fabricated in CMOS and there is intrinsic latch-up problem associated with any CMOS devices, proper power-up sequence can reduce the danger of triggering latch-up. When powering up the system, control logic power must be powered on first. When powering down the system, control logic must be shut off later than or at the same time with the LCD bias (VEE).
1 second (minimum) 5V
1 second (minimum)
VDD
0V 0~50 ms 0~50 ms
Signal
0 second (minimum) 0 second (minimum)
VEE
-30V
Fig.35 Recommended power up/down sequence 2. The metal frame of the LCD panel should be grounded. 3. A 0.1 F ceramic capacitor should be connected between VDD and VSS. 4. A 0.1 mF ceramic capacitor should be connected between VDD (or VSS) and each of V1, V2, V3, V4, and V5. 5. If the length of the cable connecting the host microcontroller and the LCD module is longer than 45 cm, a ceramic capacitor of 20P~150P should be connected between VDD (or VSS) and each of the R/WR(WR), the E/RD, and the CS.
2006 Aug 16
49 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
20 PACKAGE INFORMATION
Pakage information is provided in another document. Please contact Avant Electronics for package information.
2006 Aug 16
50 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
21 SOLDERING 21.1 Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. For more in-depth account of soldering ICs, please refer to dedicated reference materials. 21.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, please contact Avant for drypack information. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 21.3 Wave soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Repairing soldered joints
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2006 Aug 16
51 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
22 LIFE SUPPORT APPLICATIONS Avant's products, unless specifically specified, are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Avant customers using or selling Avant's products for use in such applications do so at their own risk and agree to fully indemnify Avant for any damages resulting from such improper use or sale.
2006 Aug 16
52 of 52
data sheet (v6.3)

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